Semiconductor devices such as MOSFETs have been used in power electronics applications due to their appreciable off-state voltage blocking capability and on-state current carrying capacity with low on-state resistance RDSON. In terms of industrial applications, power MOSFET devices are commonly used in many electronics fields such as portable electronics, power supplies and telecommunications and more particularly in many industrial applications relating to automotive electronics.
Conventionally, an insulated gate FET (IGFET) configuration for a power MOSFET has a four-layer structure of alternating p-type and n-type doping superposed vertically in the body of the semiconductor die, that is to say superposed in a direction perpendicular to the main faces of the die. An example of this type of structure is the n+pn−n+ structure termed enhancement mode n-channel MOSFET. Source and gate electrodes are positioned in arrays of cells at one face of the device, the source electrodes contacting the source regions formed at the substrate surface in the first n+ layer and the gates being disposed over base regions in the p layer, insulated from the semiconductor material by an oxide or other insulating layer. One or more drain electrodes are disposed at the opposite face of the device contacting the opposite n+ layer in the substrate. By applying a voltage higher than a threshold level, which biases the gate positive with respect to the source, an n-type inversion layer or channel will be formed in the base regions under the gate oxide layer through the p-type layer of the cells, thus forming a connecting layer between the source and the drain regions and allowing a current to flow. Once the device is turned on, the relation between the current and the source-drain voltage is nearly linear which means that the device then behaves like a resistance. The on-state resistance RDSON should be as low as possible.
A high cell density insulated gate IGFET configuration is preferred because of the low on-state resistance per unit area it offers. An example of high cell density vertical IGFET configurations is given in U.S. Pat. No. 6,144,067, which describes a power MOS gated device with a strip gate poly structure to increase channel width while reducing the gate resistance. Other examples of IGFET are described in international patent applications WO 01/31711 and WO 01/31709, in which a single continuous base region has an undulating structure; both devices implement a single well region made by a layout where either the gate layer substantially surrounds the base region, or the base region, which is composed of a plurality of branches, substantially surrounds the gate layer of the transistor. U.S. Pat. No. 5,703,389 describes a vertical IGFET configuration having a stripe configuration wherein the stripe regions have a non linear shape that leads to an increase of the channel density.
European patent specification EP 1 387 408 describes a low on-state resistance power semiconductor device in which each individual cell comprises a plurality of radially extending branches having source regions within base regions, at least one branch of each cell extending towards at least one branch of an adjacent cell; the base regions of the extending branches are merged together to form a single and substantially uniformly doped base region well surrounding drain islands at the surface of the semiconductor substrate. Other semiconductor devices having base regions common to an array of cells are described in European patent specifications EP 0 655 787 and EP 0 827 209.
In spite of the various design features adopted, a problem that increases with increasing the cell or channel density is maintaining or improving the breakdown voltage. The different configurations referred to above address the issue of breakdown voltage but there remains a conflict between reducing on-state resistance, especially by increasing the channel density, and improving breakdown voltage.